1. Field of the Invention
The present invention relates to an A/D (analog-to-digital) converter and, more specifically, to a successive approximation type A/D converter.
2. Description of Related Art
Demands for improving the accuracy and operation speed of a successive approximation type A/D converter are increased more and more. The successive approximation type A/D converter is provided with a built-in voltage comparator. It is preferable that the built-in voltage comparator has a high gain and a low offset in order to achieve an accurate A/D conversion by the successive approximation type A/D converter. Further, it is preferable that the built-in voltage comparator operates at a high speed in order to achieve high-speed A/D conversion.
In designing the voltage comparator, attention should be paid a trade-off relation between the offset and the operation speed. In order to keep a small offset, it is necessary to design a device size to be large. However, an increase in the device size causes an increase in a parasitic capacitance, which makes it difficult to improve the operation speed of the voltage comparator. Further, when the element size is designed to be large, a core size becomes increased, which results in increasing a chip size as well.
For overcoming such problems, a technique is known that corrects the offset of the voltage comparator by adding and controlling a capacitance element used for correction (for example, see Japanese Patent Application Publication (JP-A-Heisei 7-86947).
FIG. 1 is a circuit block diagram showing a configuration of an A/D converter disclosed in Japanese Patent Application Publication (JP-A-Heisei 7-86947). The A/D converter shown in FIG. 1 is a successive approximation type A/D converter which includes a higher 10-bit capacitance array and has 10-bit resolution. As shown in FIG. 1, an analog input voltage signal Ain 101, an upper-limit reference voltage (VT) 102, and a lower-limit reference voltage (VB) 103 are supplied to the successive approximation type A/D converter.
The successive approximation type A/D converter includes a sample voltage supplying line 104, a first switch 105, a main capacitance array 106, a correction capacitance array 107, a main switch group 108, a correction switch group 109, a common connection node 110 of the capacitance arrays, a voltage comparator 111, a successive approximation register SAR 114, a main switch control circuit 116, a correction switch control circuit 117, a first buffer 118, a first data bus 115, a latch circuit 140 for storing a correction data, and a first data bus 141 for supplying the correction data from the latch circuit 140 to the correction switch control circuit 117.
The first switch 105 is connected to an analog ground line AGND 130. The first switch 105 selects one of the analog input voltage signal 101 and the analog ground voltage signal 130, and supplies it to the sample voltage supplying line 104. The voltage comparator 111 includes a second switch 112 and an amplifier 120. The second switch 112 sets the voltage comparator 111 to an operating point. The voltage comparator 111 outputs a comparison result 113. The first data bus 115 supplies a value of the successive approximation register 114 to the main switch control circuit 116, the correction switch control circuit 117, and the first buffer 118. The first buffer 118 outputs a final A/D conversion result (A/D conversion result 119). The main switch control circuit 116 outputs a main switch control signal 124. The correction switch control circuit 117 outputs a correction switch control signal 123.
A control circuit 134 controls the first switch 105, the main switch control circuit 116, the correction switch control circuit 117, the latch circuit 140, the voltage comparator 111, the successive approximation register 114, and the first buffer 118. A clock signal 131 for operating the control circuit 134 is supplied to the control circuit 134. Further, the control circuit 134 is supplied with an A/D trigger 132 as a control signal to instruct to start an A/D conversion and a calibration external trigger 133 as the control signal to instruct to start an A/D conversion for detecting an offset error.
The control circuit 134 outputs a signal EOC 121 indicating an end of the A/D conversion, a signal TCG 122 to indicating a sampling period, and a control signal 135. The control signal 135 outputted from the control circuit 134 is a control signal for controlling circuit blocks, such as the first switch 105, the main switch control circuit 116, the correction switch control circuit 117, the latch circuit 140, the voltage comparator 111, the successive approximation register 114, and the first buffer 118.
An internal D/A converter of the A/D converter shown in FIG. 1 includes the main capacitance array 106. The main capacitance array 106 includes 11 binary-weighted capacitance elements. That is, the main capacitance array 106 includes capacitance elements C00 and C0 having a capacitance value (1C) of a unit capacitance element, a capacitance element C1 having a capacitance value that is 21 times of the unit capacitance element, and also capacitance elements of C2- C9 having capacitance values of 22 times to 29 times.
Further, the A/D converter includes a correction internal D/A converter (the correction capacitance array 107). The correction capacitance array 107 includes 7 binary-weighted capacitance elements. That is, the correction capacitance array 107 includes capacitance elements CC00 and CC0 having a capacitance value (1C) of a unit capacitance element, a capacitance element CC1 having a capacitance value that is 21 times of the unit capacitance element, and also capacitance. elements of CC2-CC5 having capacitance values of 22 times to 25 times. Therefore, this A/D converter can perform correction of the offset error with 6-bit resolution.
Details of the control circuit 134 and the control signal 135 will be described with reference to FIG. 2. A counter 201 counts the sampling period. The counter 201 starts a counting operation in response to the clock signal 131 when a count start setting signal 208 is set to a high level. Further, a trigger detecting circuit 202 detects that a calibration external trigger (instructing to start A/D conversion for detecting an offset error) 133 is set to the high level. An OR circuit 203 recognizes that either the A/D trigger (instructing to start A/D conversion) 132 or the calibration external trigger (instructing to start A/D conversion for detecting the offset error) 133 is set to the high level.
A second buffer output signal 210 is a control signal to activate the second switch 112 during the sampling period. A second buffer 204 buffers and outputs the second buffer output signal 210. A third buffer output signal 211 is a control signal to connect the main switch group 108 to the side of a sample voltage supplying line 104 during the sampling period.
The first switch 105 buffers and outputs the third buffer output signal 211. A first logic circuit output signal 212 is a control signal to connect the first switch 105 to an Ain side during the sampling period. A first logic circuit 206 outputs the first logic circuit output signal 212.
A second logic circuit output signal 213 is a control signal to connect the first switch 105 to an AGND side. A second logic circuit 207 outputs the second logic circuit output signal 213. The count start setting signal 208 is a signal for setting a start of the counting operation by the counter 201 based on an output signal of the OR circuit 203. A trigger detecting circuit output signal 209 is an output signal of the trigger detecting circuit 202. The trigger detecting circuit output signal 209 is supplied to the first logic circuit 206 and the second logic circuit 207, and controls whether to connect the first switch 105 to the Ain side or to the AGND side. Further, the trigger detecting circuit output signal 209 is supplied to the latch circuit 140, the main switch control circuit 116, the correction switch control circuit 117, and the first buffer 118, and is used to control whether to use the value of the first data bus 115 from the successive approximation register SAR 114 in the main switch control circuit 116 or in the correction switch control circuit 117, and to control whether to output the value from the first buffer 118 as the A/D conversion result 119 or to store it to the latch circuit 140.
Now, a basic operation of the A/D converter (to be referred to as A/D converting operation hereinafter) will be described. FIG. 3 is a timing chart for showing the operation of the A/D converter. This timing chart shows the operation of the A/D converter when correction of an offset error is not taken into consideration.
Referring to FIG. 3, the A/D converting operation is started by setting the A/D trigger (instructing to start an A/D conversion) 132 to the high level. When the A/D trigger 132 turns to the high level, the counter 201 starts a counting operation. The counter 201 outputs a TCG signal (indicating the sampling period) 122 in the high level until the counting operation during the sampling period ends. In FIG. 3, this period is shown as TCG. The A/D converter performs sampling of the analog input voltage signal Ain in the TCG period.
At this time, the second switch 112 of the voltage comparator 111 is activated in response to the second buffer output signal 210. When the second switch 112 is activated, the voltage comparator 111 biases the voltage of the common connection node 110 of the capacitance arrays to a constant voltage (VCOM). The first switch 105 connects the analog input voltage supplying line for supplying the analog input voltage signal Ain 101 to the sample voltage supplying line 104 in response to the first logic circuit output signal 212. Further, the main switch group 108 connects all the switches to the side of the sample voltage supplying line 104 in response to the third buffer output signal 211.
FIG. 4 is a schematic diagram showing the connection state at that time. As shown in FIG. 4, all the capacitance elements of the main capacitance array 106 are charged to the analog input voltage signal Ain 101 during the sampling period.
Returning to FIG. 3, the operation after the sampling period will be described. When a counting operation during a prescribed sampling period (a time of two clocks in FIG. 3) is completed, the counter 201 outputs a TCG (signal indicating the sampling period) 122 in the low level. In response to the TCG 122, the control circuit 134 outputs the second buffer output signal 210, the third buffer output signal 211, and the first logic circuit output signal 212. The control circuit 134 inactivates the second switch 112 and the first switch 105 in response to the second buffer output signal 210, the third buffer output signal 211, and the first logic circuit output signal 212.
At this time, the voltage of the common connection node 110 of the capacitance arrays turns to a high-impedance state. Therefore, all the capacitance elements of the main capacitance array 106 continue to keep the stored electric charges. An electric charge amount Q1 kept in the main capacitance array 106 can be expressed by the following equation (1).Q1=(1C×210)×(Ain−VCOM)  (1)
Thereafter, in a period T0, the successive approximation register SAR 114 sets the logic value of a first bit (MSB) of the register itself to “1”, when the sampling period ends. The first data bus 115 transfers the logic value of “1” for data D9 in correspondence to the output of the successive approximation register SAR 114. In case of the basic A/D converting operation, the calibration external trigger (instructing to start A/D conversion for detecting an offset error) 133 remains in the low level. Thus, the correction switch group 109 of the trigger detecting circuit 202 also remains in the low level.
At this time, the main switch control circuit 116 controls the main switch group 108 so as to switch the voltage to be applied to each of the capacitance elements of the main capacitance array 106, based on a code of the first data bus 115. In the period T0, the switches S8-S0 and the switch S00 of the main switch group 108 are made contact to the side of the lower-limit reference voltage (VB), and the switch S9 is made connect to the side of the upper-limit reference voltage (VT). FIG. 5 is a circuit diagram schematically showing the circuit in such a state. Referring to FIG. 5, in the above operation, the lower-limit reference voltage (VB) is applied to a half of the capacitance of the main capacitance array 106, and the upper-limit reference voltage (VT) is applied to the remaining half of the capacitance.
At this time, an amount of electric charge Q2 stored in the main capacitance array 106 can be expressed by the following equation (2), provided that the voltage of the common connection node 110 of the capacitance arrays is VX.Q2=(1C×29)×(VT−VX)+(1C×29)×(VB−VX)  (2)
The electric charge amount Q1 stored in the main capacitance array 106 during the sampling period remains as it is. Thus, the voltage VX of the common connection node 110 of the capacitance arrays can be found by setting “Q1=Q2” from the equation (1) and the equation (2). The voltage is expressed by the following equation (3).
                    VX        =                                            (                              VT                +                VB                            )                        2                    -          Ain          +          VCOM                                    (        3        )            
The voltage (VX) of the common connection node 110 of the capacitance arrays expressed by the equation (3) and the voltage (VCOM) of the common connection node 110 of the capacitance arrays during the sampling period TCG are detected by the voltage comparator 111. As the comparison result 113, the voltage comparator 111 outputs the logic value of “1” when the voltage (VCOM) of the common connection node 110 of the capacitance arrays during the sampling period TCG is larger, and outputs the logic value of “0” for an opposite case.
When the comparison result 113 indicates the logic value of “1”, the successive approximation register SAR 114 keeps the logic value of “1” of the first bit (MSB) so as to keep the logic value of “1” for the data D9 of the first data bus 115. For the opposite case, the first bit (MSB) is set to logic value of “0” so as to set the logic value of “0” for the data D9 of the first data bus 115. Thus, in the operation, the comparing operation of the first bit (MSB) is ended.
Returning to FIG. 3 again, the successive approximation register SAR 114 sets the logic value of “1” of a second bit in a next period T1 so as to set the logic value of the data D8 of the first data bus 115 to “1”. The main switch control circuit 116 controls the main switch group 108 in accordance with the code of the first data bus 115. The main switch control circuit 116 switches the connections of the main switch group 108 so as to switch the voltage to be applied to each of the capacitance elements of the main capacitance array 106. Assuming that the comparison result of the first bit indicates the logic value of “1”, the switch S8 of the main switch group 108 is made connect to the side of the upper-limit reference voltage (VT), while the switch S9 is kept connected to the side of the upper-limit reference voltage (VT). As in case of the comparing operation of the first bit, the amount of electric charge Q1 stored in the main capacitance array 106 during the sampling period is maintained. Thus, the voltage VX of the common connection node 110 of the capacitance arrays is a voltage that is expressed by the following equation (4).
                    VX        =                                            (                              VT                +                VB                            )                        2                    +                                    (                              VT                +                VB                            )                        4                    -          Ain          +          VCOM                                    (        4        )            As in case of the comparing operation of the first bit, the voltage (VX) of the common connection node 110 of the capacitance arrays expressed by the equation (4) and the voltage (VCOM) of the common connection node 110 of the capacitance arrays during the sampling period TCG are compared by the voltage comparator 111. The successive approximation register SAR 114 determines the value of the second bit in accordance with the comparison result. A series of operations are repeated until the period T9. Data to the lowest bit (LSB) of the successive approximation register SAR 114 is outputted as the result of the A/D conversion of the analog input voltage signal Ain 101. After the period T9 has passed, the successive approximation register SAR 114 outputs an EOC 121 to indicate the end of A/D conversion. At this time, the trigger detecting circuit output signal 209 is in the low level, so that the result of the A/D conversion of the analog input voltage signal Ain 101 is outputted from the first buffer 118 as the A/D conversion result 119 in the form of a digital signal.
There is a case that the voltage comparator 111 includes an offset error. The A/D converter has a function of correcting the offset error to attain an accurate A/D conversion characteristic. Hereinafter, the A/D converting operation performed for detecting the offset error will be described with reference to a timing chart shown in FIG. 6.
Referring to FIG. 6, as in case of the basic A/D converting operation, the A/D converter performs the A/D converting operation during the sampling period TCG and the comparing periods T0-T5. The A/D converter starts the A/D converting operation in response to the calibration external trigger (instructing to start the A/D conversion for detecting the offset error) 133 to detect the offset error. Further, the voltage to be sampled is not the analog input voltage signal Ain but the analog ground voltage signal AGND. Furthermore, the D/A converter uses the correction capacitance array 107 together with the correction switch group 109 in the comparing periods.
When the calibration external trigger 133 is set to the high level, the A/D converter starts the A/D converting operation to detect the offset error. When the calibration external trigger 133 turns to the high level, the counter 201 starts a counting operation in response to the output of the OR circuit 203 at that time. The counter 201 outputs the TCG 122 in the high level in response to the start of the counting operation. The A/D converter performs sampling of the analog ground voltage signal AGND in response to the TCG 122 in the high level.
At this time, the second switch 112 is activated in response to the second buffer output signal 210. By the activation of the second switch 112, an input terminal and an output terminal of the amplifier 120 for the voltage comparator 111 are short-circuited. Thus, the voltage comparator 111 biases the voltage of the common connection node 110 of the capacitance arrays to a constant voltage (VCOM). Further, the first switch 105 connects the sample voltage supplying line 104 to the side of the analog ground voltage signal AGND in response to the second logic circuit output signal 213. Further, the main switch group 108 connects all the switches to the side of the sample voltage supplying line 104 in response to the third buffer output signal 211. Thus, all the capacitance elements of the main capacitance array 106 are charged to the analog ground voltage signal AGND.
At this time, the correction switch control circuit 117 outputs the correction switch control signal 123 to apply the constant voltage to the correction capacitance array 107. FIG. 7 is a circuit diagram showing a configuration of the main capacitance array 106 and the correction capacitance array 107 at that time. In FIG. 7, the upper-limit reference voltage (VT) is applied to a half of the capacitance of the correction capacitance array 107 and the lower-limit reference voltage (VB) is applied to the remaining half of the capacitance so as to set to an intermediate value of a correction range.
When the counting operation of a prescribed sampling period ends, the counter 201 outputs the TCG 122 in the low level. In accordance with the second buffer output signal 210 and the second logic circuit output signal 213 outputted in response to the TCG 122 in the low level, the second switch 112 and the first switch 105 are turned OFF. At this time, the voltage of the common connection node 110 of the capacitance arrays turns to a high-impedance state. Thus, the electric charges that are stored in all the capacitance elements of the main capacitance array 106 and the correction capacitance array 107 remain as it is.
Thereafter, the correction switch control circuit 117 applies to each of the capacitance elements of the main capacitance array 106, the voltage corresponding to the code (theoretical value) indicating the analog ground voltage signal AGND in the period T0. Further, the successive approximation register SAR 114 sets the logic value of the first bit to “1”. Here, the correction capacitance array 107 is used in the comparing period of the A/D converting operation to detect the offset error. The correction capacitance array 107 is of 6 bits. Thus, the successive approximation register SAR 114 functions as a 6-bit register. FIG. 8 shows a circuit diagram schematically showing the configuration.
The first bit of the successive approximation register SAR 114 corresponds to the data D5 that is supplied via the first data bus 115. By setting the logic value of the first bit of the successive approximation register SAR 114 to “1”, the logic value of the data D5 is set to “1”. The latch circuit 140 outputs the data, which is supplied via the first data bus 115, to the second data bus 141 as it is. The correction switch control circuit 117 controls the correction switch group 109 based on the code supplied via the second data bus 141. The correction switch group 109 changes the voltage to be applied to each of the capacitance elements of the correction capacitance array 107 in response to the correction switch control signal 123 outputted from the correction switch control circuit 117.
Thus, when the voltage of the common connection node 110 of the capacitance arrays changes, the voltage comparator 111 compares the voltage after the change and the voltage of the common connection node 110 of the capacitance arrays during the sampling period TCG. The voltage comparator 111 outputs the comparison result 113 to indicate the logic value of “1”, when the voltage of the common connection node 110 of the capacitance arrays during the sampling period TCG is higher. Meanwhile, the voltage comparator 111 outputs the comparison result 113 to indicate the logic value of “0” for the opposite case. When the logic value of the comparison result 113 is “1”, the successive approximation register SAR 114 keeps the logic value of the first bit to be “1”. When the logic value of the comparison result 113 is “0”, the successive approximation register SAR 114 changes the logic value of the first bit to “0”.
The same operation is repeated in the same manner from the period T1 to the period T5. The data from the successive approximation register 114 to the lowest bit (LSB) is the offset error data. After the period T5 has passed, the successive approximation register SAR 114 outputs an EOC 121. At this time, the trigger detecting circuit output signal 209 is in the high level, so that the successive approximation register SAR 114 stores the error data in the latch circuit 140 as the correction data.
Next, an A/D conversion operation for correcting the offset error will be described with reference to a timing chart shown in FIG. 9. As in case of the basic A/D converting operation, the operation for correcting the offset error is performed during the sampling period TCG and the comparing periods T0-T9, in which the offset error is corrected based on the detected offset error data.
The A/D converting operation is started by setting the A/D trigger (instructing to start the A/D conversion for detecting the offset error) 132 to the high level. When the calibration external trigger (instructing to start the A/D conversion for detecting the offset error) 133 turns to the high level, the counter 201 starts a counting operation in response to the output of the OR circuit 203 at that time. The counter 201 outputs the TCG 122 in the high level in response to the start of the counting operation. The counter 201 continues to output the TCG 122 in the high level, until the counting operation of the sampling period is ended. The A/D converter performs sampling of the analog ground voltage signal AGND in response to the TCG 122 in the high level.
The second switch 112 is activated in response to the second buffer output signal 210. Thus, the voltage comparator 111 biases the voltage of the common connection node 110 of the capacitance arrays to a constant voltage VCOM. Further, the first switch 105 connects the analog input voltage signal Ain 101 to the sample voltage supplying line 104 in response to the first logic circuit output signal 212. All of the switches of the main switch group 108 connect the sample voltage supplying line 104 to the main capacitance array 106 in response to the third buffer output signal 211. All the capacitance elements of the main capacitance array 106 are charged to the analog input voltage signal Ain. At this time, the same constant voltage as the voltage applied at the time of offset error detection is applied to the correction capacitance array 107.
FIG. 10 is a circuit diagram schematically showing a configuration of the circuit in such a state. For example, the upper-limit reference voltage (VT) is applied to a half of the capacitance of the correction capacitance array 107 and the lower-limit reference voltage (VB) is applied to the remaining half of the capacitance thereof so as to set to an intermediate value (the intermediate value “32” in case of FIG. 1, since the correction capacitance array 107 is of 6 bits) of a correction range.
When the counting operation during a prescribed sampling period ends, the counter 201 sets the TCG 122 to the low level. In response to the TCG 122 in the low level, the second switch 112 and the first switch 105 are inactivated. At this time, the voltage of the common connection node 110 of the capacitance arrays turns to a high-impedance state. Thus, the electric charges that are stored in all the capacitance elements of the main capacitance array 106 and the correction capacitance array 107 are kept. An amount of electric charge Q3 stored at this point can be expressed by the following equation (5).Q3=(1C×210)×(Ain−VCOM)+(1C×25)×(VT−VCOM)+(1C×25)×(VB−VCOM)  (5)
Thereafter, the control circuit 134 applies the voltage to the correction capacitance array 107 in accordance with the offset error stored in the latch circuit 140 in the comparing periods T0-T9. Assuming that the correction code of the offset error is the voltage for 40 LSB (the actual correction amount is the voltage for 8 LSB, which is obtained by subtracting the intermediate value set during the sampling period TCG (40 LSB−32 LSB=8 LSB)), the correction switch control circuit 117 applies the upper-limit reference voltage (VT) to the capacitance element CC5 corresponding to 25 times of the unit capacitance element and the capacitance element CC3 corresponding to 23 times of the unit capacitance element, and applies the lower-limit reference voltage (VB) to the remaining capacitance elements.
Further, the control circuit 134 sets the logic value of the first bit (MSB) of the successive approximation register SAR 114 in the period T0 to “1” so as to set the logic value of the data D9 of the first data bus 115 to “1”. In accordance with the code of the first data bus 115, the main switch control circuit 116 controls the main switch group 108. The voltages to be applied to the respective capacitance elements of the main capacitance array 106 are changed by changing the connections of the main switch group 108.
In the period T0, the switches S8-S00 of the main switch group 108 are connected to the side of the lower-limit reference voltage (VB), and the switch S9 is connected to the side of the upper-limit reference voltage (VT). FIG. 11 is a circuit diagram schematically showing the circuit in such a state. Referring to FIG. 11, the lower-limit reference voltage (VB) is applied to a half of the capacitance of the main capacitance array 106, and the upper-limit reference voltage (VT) is applied to the remaining half of the capacitance.
At this time, an amount of electric charge Q4 stored in the main capacitance array 106 and the correction capacitance array 107 can be expressed by the following equation (6), provided that the voltage of the common connection node 110 of the capacitance arrays is VX.Q4=(1C×29)×(VT−VX)+(1C×29)×(VB−VX)+{1C×(25+23)}×(VT−VX)+{1C×(20+20+21+22+24)}×(VB−VX)  (6)
The amount of electric charge Q3 stored in the main capacitance array 106 and the correction capacitance array 107 during the sampling period remains as it is. Thus, the voltage (VX) of the common connection node 110 of the capacitance arrays can be found by setting “Q3=Q4” from the equation (5) and the equation (6), and the voltage is expressed by the following equation (7).
                    VX        =                                            (                                                2                  10                                                                      2                    10                                    +                                      2                    6                                                              )                        ×                          (                                                                    VT                    +                    VB                                    2                                -                Ain                +                                  8                  ⁢                  LSB                                            )                                +          VCOM                                    (        7        )            
As in the equation (7), it can be found that the voltage for the correction data (8 LSB) of the offset error has being corrected. The voltage (VX) of the common connection node 110 of the capacitance arrays expressed by the equation (7) and the voltage (VCOM) of the common connection node 110 of the capacitance arrays during the sampling period TCG are compared by the voltage comparator 111. The voltage comparator 111 outputs the logic value of “1” as the comparison result 113 when the voltage (VCOM) of the common connection node 110 of the capacitance arrays during the sampling period TCG is higher, and outputs the logic value of “0” as the comparison result 113 for the opposite case.
When the logic value of the comparison result 113 is “1”, the successive approximation register SAR 114 keeps the logic value of the first bit (MSB) to be “1” so as to keep the logic value of “1” for the data D9 of the first data bus 115. For the opposite case, the first bit (MSB) is set to the logic value of “0” so as to set the logic value of “0” for the data Dg of the first data bus 115. Thus, in this operation, the comparing operation of the first bit (MSB) is ended.
The operation in the period T1 and the subsequent is the same as the basic A/D converting operation. The data to the lowest bit (LSB) of the successive approximation register SAR 114 is obtained as the result of the A/D conversion on the analog input signal Ain, and it is outputted as the A/D conversion result 119 with the offset error being corrected.
However, there is a limit in a voltage range that can be corrected by the correction capacitance elements. Thus, in order to extend the correctable voltage range, it is necessary to increase the correction capacitance elements. However, this causes an increase in a core size for the increase in the correction capacitance elements.